Job Description and Requirements
Circuit STA Timing Closure Engineer
The Circuit STA Timing Closure Engineer will be responsible for delivering best quality custom circuit timing models to the place and route (P&R) team. This position requires hands on experience with static timing analysis (STA) tools and flows (PrimeTime, NanoTime) with some knowledge of mixed signal circuit design principles. The responsibilities include delivering timing models, improving our STA flow, identifying design vs flow issues, working closely with cross functional teams to control quality of internal timing and solving any issues at the interface between mixed signal circuit and P&R digital hardware.
This position is also responsible for black box extraction, timing characterization of analog circuit within black box, developing and maintaining timing constraints for STA flow on mixed signal circuits, evaluating and fixing timing violations, closing circuit level internal timing, timing correlation between STA and extraction tools, participate/contribute in timing expert meetings/reviews and publishing timing status after each milestones with quality checks.
This position requires good technical hold of timing expertise and responsible for understanding all aspects of timing
This position is responsible for technical leadership, review, sign off of timing constraints, timing arcs and review changes/results etc before releasing to Customers.
The responsibility also includes ownership and deployment of new timing flows, driving and assisting team in technical debug and resolution.
This position requires strong scripting skills to automate checks and the ability to lead and train junior engineers to become experts in timing.
MTech/BTech/Ph.D. and 7+ years relevant experience preferred (or equivalent education and experience).
Solid understanding of static timing concepts and engineering fundamentals.
Strong expertise in transistor-level design simulation/verification (HSPICE/Finesim) to debug circuit level issues with waveforms.
Experienced in physical verification to debug LVS issues at block and top level.
Experienced in STAR or similar extractor to debug extraction issues.
Good understanding of hierarchical design, blackbox, and selected nets extractions.
Strong skills with Synopsys SiliconSmart, NantoTime and PrimeTime.
Experience in advanced technology nodes preferred.
Good knowledge of TCL, Perl and other scripting languages.
Good communication and interpersonal skills.
Transistor based STA experience.
SiliconSmart experience highly desirable.
NanoTime / Primetime experience highly desirable.
CCS timing and noise model generation experience.