Job Description

Responsibilities:

• Develop and execute verification plans for complex SOC designs, including defining test strategies, creating test benches, and developing test cases.
• Collaborate with the design team to understand the SOC architecture and specifications.
• Implement and maintain scalable and reusable verification environments using industry-standard methodologies (such as UVM, SystemVerilog).
• Write and debug testbench components, stimulus, and test sequences.
• Perform functional and performance verification of SOC designs, including running simulations, running regressions, and analyzing results.
• Debug and isolate design issues, work closely with the design team to resolve them, and track bug resolution.

Requirements:

• Minimum 5 years of experience
• Basic Requirement: Strong in SV, UVM,
• Having protocols knowledge on PCIE, Ethernet, DDR, GLS
• Knowledge of from-scratch level Verification, Writing tests, and developing test benches